Various example embodiments relate to a nonvolatile memory device, and more particularly, to a nonvolatile memory device for controlling a program-verify operation according to a noise level of a common source line, a method of operating the same and an electronic device including the same.
Semiconductor memory device includes a volatile memory device and a nonvolatile memory device. The volatile memory device includes a dynamic random access memory (DRAM), a static random access memory (SRAM) and etc. The nonvolatile memory device includes a flash memory, Electrically Erasable Programmable Read-Only memory (EEPROM), a resistive memory and etc.
Flash memory includes a memory cell array which stores data. The memory cell array includes a plurality of memory blocks each of which includes a plurality of pages. Each of the pages includes a plurality of memory cells.
The memory cells are classified as on-cells and off-cells according to the distribution of their threshold voltages. The flash memory may perform an erase operation in units of memory blocks and may perform a program operation or a read operation in units of pages.
The flash memory includes a cell string structure. A cell string includes a plurality of transistors connected in series between a string selection transistor connected to a string selection line (SSL) and a ground selection transistor connected to a ground selection line (GSL). The string selection transistor is connected to a bit line and the ground selection transistor is connected to a common source line (CSL).
Each of the memory cells may be implemented by a single level cell (SLC) storing a single bit or a multi-level cell (MLC) storing a plurality of bits. The MLC has an erased state and a plurality of programmed states according to its threshold voltage. It is important to the MLC to narrow the width of a threshold voltage distribution of each programmed states so that a margin for the programmed state is secured. CSL noise may cause the width of the threshold voltage distribution for each programmed state to increase.
The CSL noise signifies an increase of the voltage of the CSL due to current flowing in an on-cell during the read operation or the program-verify operation. When the voltage of a source node of the ground selection transistor may increase due to the CSL noise, current flowing in the on-cell is decreased even through a word line voltage or a bit line voltage does not change. As a result, the threshold voltage of the on-cell is increased, and therefore, the on-cell may be wrongly determined as an off-cell. This wrong determination causes errors in the read operation or the program-verify operation.